As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical transport field effect transistors (VTFETs) are oriented with a vertical fin channel disposed on bottom source and drains and a top source and drain disposed on the vertical fin channel. A gate runs vertically alongside the vertical fin channel.
A replacement metal gate process for FETs is beneficial as it permits gate metal workfunction customization and tuning. However, there are notable challenges associated with a replacement metal gate process and the VTFET design. Namely, the device is built from the bottom up, with the top source and drains being grown in top of the channel after the gate has been formed. The elevated temperatures (e.g., exceeding 600° C.) associated with the top source and drain formation can degrade a conventional replacement metal gate. For instance, at temperatures greater than or equal to about 600° C., conventional n-channel VTFET designs undesirably experience a dramatic increase in leakage current while p-channel VTFET designs undesirably experience a threshold voltage (Vt) increase.
Therefore, thermally stable replacement metal gate stack designs for a VTFET architecture would be desirable.